This invention relates to a circuit arrangement for storing sampled analogue electrical currents.
The switched capacitor technique has been used for processing analogue signals using circuitry which can be easily integrated. It is difficult to integrate large valued resistors because of the area occupied thereby and further the correlation between resistor and capacitor values produced by integration is not good, causing the resultant time constants to be poorly defined. Therefore, the technique of using the equivalent resistance of a capacitor which is switched into and out of circuit to cause processing to take place by means of manipulation of charge packets has been used for analogue signal processing where integration has been required.
Although they are widely used, switched capacitor circuits have certain disadvantages. It is necessary to produce capacitors which are linear, that is their capacitance should not change significantly with the signal level. This has been achieved in CMOS integrated circuits by providing two polysilicon layers for the plates of the capacitors. However, standard CMOS processes used for the integration of digital circuits do not employ a double polysilicon layer. Consequently, switched capacitor circuits which are formed on the same chip as digital circuits require additional processing steps. In switched capacitor circuits the double polysilicon layer switched capacitors together with the required compensation capacitors for the operational amplifiers can account for a significant proportion of the total silicon area. This tends to produce relatively large chips. Further, in most switched capacitor systems, each amplifier and switch must be individually designed and optimised for its particular environment in order for the circuit to perform adequately.
My co-pending application No. 8721758, which corresponds to copending U.S. Appln. Ser. No. 244,440, filed Sept. 14, 1988, discloses a method of processing sampled analogue electrical signals comprising the steps of
(a) converting each sample into a current, if it is not already in that form;
(b) combining, in predetermined proportions, the input sample current in the present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods, and
(c) deriving the processed output signal from the combined current produced by step (b) in successive sample periods.
This method is based on the realisation that the quantity manipulated can be current rather than, as is the case with switched capacitor circuits, charge. The choice of current as the manipulated variable quantity rather than charge characterises the method. Thus, in a switched capacitor circuit the signal processing is achieved by adding, subtracting or storing electrical charges, whereas in the method set out hereinbefore, referred to hereinafter as switched current signal processing, the signal processing is achieved by scaling, adding, subtracting or storing electrical current samples. Considerable similarities exist in the processing of the electrical quantities although the actual electrical quantity manipulated is different. In particular, all of the mathematics concerned with the application of Z-transforms to switched capacitor circuits is equally valid for those employing current as the manipulated quantity.
The choice of current as the manipulated quantity provides a number of advantages. The technique does not require high quality linear capacitors. As a direct consequence, it may be possible to dispense with the second polysilicon layer used in switched capacitor circuits to fabricate linear capacitors. In that case standard CMOS processes used for the integration of digital circuits may be used for the implementation of circuits employing the method. This gives true VLSI compatibility. Since the large area double polysilicon layer switched capacitors are not required and the only requirement for capacitors for the new method is for capacitors which have a small value and have a monotonic charge/voltage relationship which need not be linear and which may be realised as gate oxide or diffusion capacitors. Thus, for a given function the implementation will be smaller than its switched capacitor counterpart. Further reduction in the chip area may also result from the use of smaller geometry MOS processes. Circuits designed in older, coarser, processes may be able to take advantage of developments in mask making and etching technologies by geometric shrinkage of the layout. Geometric shrinkage is not generally feasible in switched capacitor circuits since circuit parameters, such as amplifier settling time and switch resistance, can change detrimentally even though the channel width/length ratio of the MOS devices is held constant.
In a switched capacitor system, each amplifier and switch must be individually designed and optimized for its particular environment in order for the circuit to perform adequately. In contrast, the nature of operation of the switched current signal processing method requires only two basic circuit elements, that is a family of low input impedance high output impedance current mirrors and analogue current memory, which need be designed once only for each IC process. It will, of course, be necessary to design a separate current mirror for each scaling factor. Thus, once a particular system configuration has been decided upon, the time spent on circuit design for implementation of the new technique may be significantly reduced compared with that required for a switched capacitor approach. The independent cellular nature of the circuitry enabled by the switched current signal processing method opens the way for semi-custom design procedures to be applied.
The principal disadvantage of this method is a consequence of its discrete time operation. As in a switched capacitor signal processing system or any system in which signal sampling is performed, some form of anti-aliasing filtering is required before the first sample and hold operation. Apart from representing an increase in complexity of total circuit function, the VLSI compatibility of the technique is threatened if the anti-alias filter requires a second polysilicon layer or other process modification for its monolithic implementation.